interrupt coalescing / polling

[Donald Becker]

On Fri, 26 Feb 1999, John Plevyak wrote:
> On Fri, Feb 26, 1999 at 02:48:41AM -0500, Donald Becker wrote:
> > On Thu, 25 Feb 1999, John Plevyak wrote:
> > Unlike most chips the EEPro100 has only a global interrupt mask, not
> > individual interrupt enables.  You would have to turn off the interrupt bits
> > on the receive descriptor list.

Ooops, I was wro.. wron.. wr.. wrr..  ..your understanding of my statement was
limited ;->
Specific interrupts, including the RxDone interrupt, on the Speedo3
(EEPro100B chip) can be masked.
There is an Rx indication for every received frame.
  (Definition: "Indication" means "will generate an interrupt if not masked")

/* Current, bits defined in the driver.*/
________________
#define INT_MASK	0x0100
#define DRVR_INT	0x0200		/* Driver generated interrupt. */
________________

/* The full list, which I'll add to the driver RSN. */
________________
enum SCBCmdBits {
     SCBMaskCmdDone=0x8000, SCBMaskRxDone=0x4000, SCBMaskCmdIdle=0x2000,
     SCBMaskRxSuspend=0x1000, SCBMaskEarlyRx=0x0800, SCBMaskFlowCtl=0x0400,
     SCBTriggerIntr=0x0200, SCBMaskAll=0x0100,
     /* The rest are Rx and Tx commands. */
     CUStart=0x0010, CUResume=0x0020, CUStatsAddr=0x0040, CUShowStats=0x0050,
     CUCmdBase=0x0060,	/* CU Base address (set to zero) . */
     CUDumpStats=0x0070, /* Dump then reset stats counters. */
     RxStart=0x0001, RxResume=0x0002, RxAbort=0x0004, RxAddrLoad=0x0006,
     RxResumeNoResources=0x0007,
};
________________

Note that the only the upper four interrupt masks bits match the SCBStatus
bits!!!


Donald Becker					  becker@cesdis.gsfc.nasa.gov
USRA-CESDIS, Center of Excellence in Space Data and Information Sciences.
Code 930.5, Goddard Space Flight Center,  Greenbelt, MD.  20771
301-286-0882	     http://cesdis.gsfc.nasa.gov/people/becker/whoiam.html