[vortex] The mysteries of on-chip MII.

[Bill Cattey]

Off-list, I have worked with Bogdan Costescu and have a tool
that can stomp on the EEPROM values to take our 3Com NICs with the
on-chip MII, and get them responding.

Bogdan's explanation of what's going on (or mor accurately what's
failing to go on) bears repeating:

    Using the setup sequence present in 3c59x (which I think it's a good
    one according to the documentation that I have) the MII registers
    seem not to be accessible if EEPROM on your cards does not contain
    NWAY/Autonegotiate. The documentation doesn't say a word about this
    situation; it says that on Cyclone and later chips (yours included)
    the MII interface with NWAY capabilities is always present as it's
    integrated on the chip, as opposed to older designs where it was an
    external chip. So, my guess is that either there is a magic sequence
    that can make the MII registers available (which we don't know) or
    that the media management in this case is not done through MII
    registers but through the older mechanism which involved writting to
    other registers in the chip; the third possibility - that I'm
    missing something - can also be taken into consideration... 8-)

It seems like we have three choices here:

1. Live with the fact that we have chips that will come from the factory
with EEPROM defaults that cause our drivers to be unable to properly
initialize the MII.

2. Contact whatever 3Com liaison negotiated their generous disclosures
of the past and say, "We've stumbled on an undocumented case that makes 
Linux configure your chips in a pathological way yielding 6KB throughput
on a 100Kb network.  Could we please have a little help getting over this
bump so that the past good work with regards to Linux is preserved?"

3. Attempt to guess at an interpretation of the documentation that
resolves this case.

----

With the tool that Bogdan supplied, I'm in a postition to choose option
1, but that's really not my preference.  I'd like to help out in moving
forward on choice 2 or 3.

With regards to #2, do you need someone to do leg work and make phone
calls and grind through the process, or is there already some sort of
ongoing communication in place?

With regards to #3 I ask what may be a naive question:  What kind of
reset sequence might one need if one first needed to verify that there
were no EXTERNAL chips active for MII?  Perhaps the assertion "the MII
interface with NWAY capabilities is always present as it's integrated on
the chip" needs to be tempered by hardware implementations that use the
new chip on legacy boards with external MII chips that are active.

In that case, could the old-style initialization be required/assumed and
a vital part of the chip reset?  (For no better reason than to activate
external chips on legacy boards first.)

What is to be done?

How can I help?

-wdc