Problem found? G-NICs and the AP450GX server.

Anthony Caola caola@MIT.EDU
Tue Nov 24 17:00:47 1998


Hello everyone -- for a couple of months, I have been having problems with 
both the Packet Engines GNIC-I and GNIC-II crashing our AP450GX server during 
bandwidth testing.  I have found that by setting the In-Order-Queue (IOQ) 
depth to 1 in BIOS, this problem appears to go away.  From the "Intel 450KX/GX 
PCIset Specification Update", it appears that this could be due to (another) 
bug in the GX chipset:

http://developer.intel.com/design/pcisets/specupdt/243109.htm
29. Hang with Zero-Byte Write Followed by a Nonzero Byte Write 
PROBLEM: If an inbound PCI zero-byte write is followed by a PCI nonzero byte 
write, and a specific set of timing circumstances exist, the chipset can 
become out of sync. This will cause DBSY# to remain asserted infinitely while 
awaiting data that will not be delivered.
IMPLICATION: When the above criteria are met, the system will hang. A hard 
reset or power cycle is required to recover from this condition.
WORKAROUND: There are two workarounds for this issue. Either set the 
In-Order-Queue (IOQ) depth to 1 or do not issue zero-byte transactions to the 
PCI bus of an 82454KX/GX PCI Bridge.

I have heard that setting the IOQ depth to 1 could adversely impact system 
performance:  Is this this the likely bug?  Do the yellowfin or hamachi 
drivers issue zero-byte transactions to the PCI bus?  Is there an easy fix 
besides just keeping the IOQ depth at 1?

Thanks for any suggestions that you have,




Anthony Caola                Massachusetts Institute of Technology
Phone:  (617) 253-6547       Department of Chemical Engineering
Fax:    (617) 258-8224       25 Ames St., Building 66-250
Email:  caola@mit.edu        Cambridge, MA  02139








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