MII reset and the sticky Link bit

[Manfred Young]

I'm the one who suggested the mdio_write code to Donald for the following
reason:

What I noticed is that occasionally after the card is reset, any reads from
the MDI registers returned FFFF. There was no way that I could get the MDI
to behave after that point, although the card continued to function
correctly, i.e. it could still send and receive packets. Incidently, the
problem only seemed to occur if the network was relatively busy. Adding the
code from lines 06 to 10 removed this problem.

> Below is a section of code from the speedo_tx_timeout routine
> in the eepro100 driver (version 1.09t) that performs a reset
> of the MII transceiver. There are several details that I don't
> understand. No, this isn't a BASIC program, I just included
> line numbers for reference.
>
> 01 /* Reset the MII transceiver, suggested by Fred Young @ scalable.com.
*/
> 02 if ((sp->phy[0] & 0x8000) == 0) {
> 03    int phy_addr = sp->phy[0] & 0x1f;
> 04    int advertising = mdio_read(ioaddr, phy_addr, 4);
> 05    int mii_bmcr = mdio_read(ioaddr, phy_addr, 0);
> 06    mdio_write(ioaddr, phy_addr, 0, 0x0400);
> 07    mdio_write(ioaddr, phy_addr, 1, 0x0000);
> 08    mdio_write(ioaddr, phy_addr, 4, 0x0000);
> 09    mdio_write(ioaddr, phy_addr, 0, 0x8000);
> 10 #ifdef honor_default_port
> 11    mdio_write(ioaddr, phy_addr, 0, mii_ctrl[dev->default_port & 7]);
> 12 #else
> 13    mdio_read(ioaddr, phy_addr, 0);
> 14    mdio_write(ioaddr, phy_addr, 0, mii_bmcr);
> 15    mdio_write(ioaddr, phy_addr, 4, advertising);
> 16 #endif
>
> line 06 - 0x0400 is being written to MDI register 0.
>    According to the Intel 82558 datasheet, this is a
>    reserved bit. Is this line an error? Is this bit
>    in fact defined somewhere? Or is another bit
>    intended here? Restart Auto negotiation? What is
>    the intention of this line of code?

Bit 10 of register 0 (the control register) is defined as Isolate:
electrically isolate the PHY from MII.

>
> line 07 - MDI register 1 is defined as Read Only (according
>    to the datasheet). Will writing to this register cause a
>    problem, or is it just ignored? What is the [intended]
>    purpose for writing to this register here?
>

All of the bits of register1 (status register) are defined as read-only, but
by trial and error I found that writing to this register is required to
avoid the problem described above.

> line 13 - According to the datasheet, for bit 15 (the reset
>    bit) "The PHY returns a value of one until the reset
>    process has completed and accepts a read or write
>    transaction." Should the result from this read be checked
>    for a one (1) before proceeding? Perhaps the subsequent
>    lines (14 and 15) need to wait for the reset to finish
>    first? And what does Intel mean by "one"? I assume this
>    means that bit 15 stays 1 and doesn't clear (become 0)
>    until the reset is complete.

We probably should wait for bit 15 to go to zero, but in my experience, I've
never had to do that.



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