MII reset and the sticky Link bit

[Yisrael]

Fred (and Donald and friends),

> I'm the one who suggested the mdio_write code to Donald for the following
> reason:

Thanks for responding.

> Bit 10 of register 0 (the control register) is defined as Isolate:
> electrically isolate the PHY from MII.

Hmmm. Where did you get this information? I can't find it anywhere.
I have the datasheet for the 558 and it says that this bit is reserved.
Is this an undocumented "feature", or am I missing some important
documentation?

In any case, this is interesting. By electrically isolating these
two units, I would imagine that this would certainly improve the
stability of the MII during reset or other control register operations.
However, well, here's the gory details...

> All of the bits of register 1 (status register) are defined as 
> read-only, but by trial and error I found that writing to this
> register is required to avoid the problem described above.
>
> We probably should wait for bit 15 to go to zero, but in my 
> experience, I've never had to do that.

I keep getting the situation that the bit just doesn't clear, no way,
no how. I check it for clearing in a loop of 100,000 and it exits
without the bit ever clearing. What am I doing wrong? In truth, I'm
using on-board 559s, not 558s, but according to Intel docs, they are
"almost" identical to the 558s. Is this my problem?

Have you seen this bit go zero? Or does your reset just work without
you're having to worrying about it?

As I see it now, the Link bit isn't the only "sticky" bit. Now it
appears that the reset bit in the control register is also "sticky".
Or perhaps it's not resetting due to some other problem.

>Incidentally, the problem only seemed to occur if the network was
>relatively busy.

This is definitely our problem. When we hit the chip hard, it sort of
rolls over and plays dead. It appears to be operational (for example
to ifconfig) but it doesn't transfer data! It just sits there like a
lump. (Sort of like me right now.)

However - the problem that I'm having above with the reset bit not
clearing is with NO traffic at all. In fact, I remove the cables
from the NICs (I'm using two on my system) before running my tests.
It immediately comes up with a "transmit timeout" message, and then
my own diagnostic printf informs me that the reset bit never clears.

I'm beginning to suspect that I really don't understand this chip.
So tell me... Am I really off-base, or do my observations make some
sense? Maybe must a little bit?

Thanks,

Yisrael (Russ) Hersch
Allot Communications
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