[tulip-bug] Admtek Comet (SMC1255TX) wierd errors on Alpha

[Donald Becker]

On Tue, 30 Apr 2002, Juhan Ernits wrote:
> On Mon, 29 Apr 2002, Donald Becker wrote:
>
> > Have you tried
> >    http://www.scyld.com/network/tulip.html
> >       ftp://www.scyld.com/pub/network/tulip.c
>
> It appears that my problem is a non-standard "feature" of the SMC1255
> card.

This appears to be a flaw in the PCI implementation.

> # this setting seems to work for SMC1255TX on ruffian alpha
> static int csr0 = 0x01A00000 | 0xA000;

Ohhhh, you have a 164UX board.
My condolences.

My 164UX board is in the mostly-broken junk bin so I can't check out
your report.  I've not seen your specific problem, but the 'UX was
plauged with memory problems.

> So, although cache alignment 32 longwords, burst length 32 longwords
> doesn't work ( csr0 = 0x01A00000 | 0xE000; ),
> cache alignment 16 longwords, burst length 32 longwords does (csr0 = 0x01A00000 | 0xA000;)

The current alpha setting shouldn't break the transfer, it should just result
in suboptimal performance.  The failure on your system might indicate a
memory problem.

> My question now is if it is possible to differentiate this setting for
> different boards on the same system within one module?

No.  The settings are influenced by the cache line attributes of the
system and should be the same for every PCI card.  Any per-device tuning
should be done with the PCI configuration space registers.

> What would be the best way to stresstest the new setting and find a kind
> of optimum?

The CSR0 register setting may be modified with the module parameter
"csr0".
  options tulip csr0=0x01A0E000

-- 
Donald Becker				becker@scyld.com
Scyld Computing Corporation		http://www.scyld.com
410 Severn Ave. Suite 210		Second Generation Beowulf Clusters
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